1. Field of the Invention
The invention relates to a DAC (Digital-to-Analog Converter)/ADC (Analog-to-Digital Converter) system, and more particularly to a DAC/ADC system for generating reference clocks by a look-up table method.
2. Description of the Related Art
FIG. 1 shows a block diagram of a conventional DAC system using the sigma-delta modulation technology. Referring to FIG. 1, the DAC system 10 includes an up-sampling unit 11, a digital low-pass filter (LPF) 12, a sigma-delta modulator 13, a DAC unit 14, and an analog LPF 15. The up-sampling unit 11 receives a digital input signal and up-samples the digital input signal to N times thereof. For example, the digital input signal, such as a x-bit PCM signal with a sampling frequency fs1, is up-sampled by the up-sampling unit 11 and generates a x-bit PCM signal with a sampling frequency N*fs1. Next, the digital LPF 12 filters out the output signal of the up-sampling unit 11 and generates an up-sampling signal with the sampling frequency N*fs1. The sigma-delta modulator 13 modulates the up-sampling signal into a y-bit modulated signal with a sampling frequency N*fs1, wherein y<x. The modulated signal further passes through the DAC unit 14 and the analog LPF 15 and becomes an analog output signal.
FIG. 2 shows a block diagram of a conventional ADC system using the sigma-delta modulation technology. Referring to FIG. 2, the ADC system 20 includes an ADC unit 21, a digital LPF 22, and a down-sampling unit 23. The ADC unit 21 samples the analog input signal using the sampling frequency of N*fs2, and generates a y-bit digital signal with a sampling frequency N*fs2. The digital signal passes through the digital LPF 22 and the down-sampling unit 23, and then becomes a x-bit digital output signal with a sampling frequency fs2, wherein y<x.
Because the DAC system 10 and ADC system 20 may use different sampling frequencies in different occasions, there must have sampling signal generators for generating different sampling frequencies. The typical sampling signal generators for generating the sampling frequency of N*fs will be described in the following.
1. A phase locked loop (PLL) or a digital phase locked loop (DPLL), for example, may directly generate the sampling signal with a sampling frequency N*fs. However, the drawback of this method is that the operation frequency of the modulator 13 is reduced as the sampling frequency is reduced, such that the high-frequency noises brought up by the modulator 13 fall within the audible range with a greater ratio. In addition, the PLL requires more circuit complexity to implement, which is not advantageous when considering system integration or fabrication technology transferring. Furthermore, the noises brought by the PLL may adversely influence the performance of the analog circuit.
2. A sigma-delta clock modulator, for instance a two-order sigma-delta clock modulator, may be used to generate the sampling signal with an average sampling frequency N*fs for the ADC unit 21 of the ADC system 20, or the modulator 13 of the DAC system 10. FIG. 3 shows the architectures of such ADC system and DAC system. Referring to FIG. 3, in addition to the elements of FIG. 1, the DAC system 30 further includes a sigma-delta clock modulator 36 for generating a reference clock with an average frequency of N*fs1. On the other hand, in addition to the elements of FIG. 2, the ADC system 30′ further includes a sigma-delta clock modulator 37 for generating a sampling clock with an average frequency of N*fs2. Therefore, in the ADC/DAC system described above, two clock modulators for generating sampling signals have to be included.